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INDEX
MX98743
FEM 100 Base Fast Ethernet Management Chip
1.0 FEATURES
* Support IEEE 802.3 MIBs * Support RMON etherStatsEnty and etherStats History group * 8/12/32 bit microprocessor interface * Linear mapped registers for easy programming * Embedded MAC for low-cost management functions implementation
2.0 GENERAL DESCRIPTION
The Fast Ethernet Management (FEM) chip works with XRC to support the following Repeater Management functions: IEEE 802.3u Port Management Attributes: - PortAdminState (from XRC, 8 port state) - AutoParitionState (from XRC, 8 port state) - ReadableFrame (32-bit Counter) - ReadableOctets (32-bit Counter) - FramesCheckSequenceError (32-bit Counter) - AlignmentErrors (32-bit Counter) - FramesTooLong (32-bit Counter) - ShortEvents (32-bit Counter) - Runts (32-bit Counter) - Collision (32-bit Counter) - LateEvents (32-bit Counter) - VeryLongEvents (32-bit Counter) - DataRateMismatches (32-bit Counter) - Auto Partitions (32-bit Counter) - Isolates (32-bit Counter) - SymbolErrorDuringPacket (32-bit Counter) - LastSourceAddress (32-bit Counter) - SourceAddressChange (32-bit Counter) IEEE 802.3u MAU Management Attributes: - FalseCarriers (32-bit Counter)
P/N:PM0413
REV.3.4, APR 14, 1997
1
INDEX
MX98743
RMON MIB Statistics Group - etherStatsDropEvents (32-bit Counter) - etherStatsOctets (32-bit Counter, same as ReadableOctets) - etherStatsPkts (32-bit Counter, same as ReadableFrames) - etherStatsBroadcastPks (32-bit Counter) - etherStatsMulticastPks (32-bit Counter) - etherStatsCRCSlignErrors (32-bit Counter, sum of FrameCheckSequenceErrors and AlignmentErrors) - etherStatsUndersizedPks (32-bit Counter, same as ShortEvent) - etherStatsOversizedPks (32-bit Counter, same as FrameTooLong) - etherStatsFragments (32-bit Counter, same as Runts) - etherStatsJabbers (32-bit Counter) - etherStatsCollision (32-bit Counter, same as Collision) - etherStatsPks64Octets (32-bit Counter) - etherStatsPkts65to127Octs (32-bit Counter) - etherStatsPkts128to255Octets (32-bit Counter) - etherStatsPks236to511Octets (32-bit Counter) - etherStatsPkts512to1023Octets (32-bit Counter) - etherStatsPkts1024to1518Octets (32-bit Counter) RMON MIB History Group The same period is programmable from 1 second to 65536 seconds. - etherHistoryDropEvents (32-bit Counter) - etherHistoryOctets (32-bit Counter, same as ReadableOctets) - etherHistoryPkts (32-bit Counter, same as ReadableFrames) - etherHistoryBroadcastPkts (32-bit Counter) - etherHistoryMulticastPkts (32-bit Counter) - etherHistoryCRCAlignErrors (32-bit Counter, sum of FrameCheckSequenceErrors and AlignmentErrors - etherHistoryUndersizedPkts (32-bit Counter, same as ShortEvent) - etherHistoryOversizedPkts (32-bit Counter, same as FramesTooLong) - etherHistoryFragment (32-bit Counter, same as Runts) - eaterHistoryCollision (32-bit Counter, same as Collision) All the above values as well as XRC registers and counters can be accessed directly through the CPU interface. The FEM occupies a contiguous 4K-byte memory space with 8-bit, 16-bit, and 32-bit datapath choices which allows system designers the maximum flexibility.
2
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MX98743
3.0 SIMPLIFIED SYSTEM DIAGRAM
uP 8/16/32
SRAM
MAC FEM MX98743 MANAGEMENT
MII Port XRC MX98741 REPEATER CONTROLLER
Figure 3-1. 8-Port Management Hub System Diagram
The FEM contains a MAC which is capable of transmitting and receiving management packets that are stored in an external SRAM. The CPU reads and writes packets in SRAM through the FEM.
3
INDEX
MX98743
4.0 CONNECTION DIAGRAM
NC CLK50M TEST MD7 MD6 MD5 MD4 VDD VDDP MD3 MD2 MD1 MD0 GNDP MWEX_ MOEX_ MSA0 MSA1 VDDP MSA2 MSA3 MSA4 MSA5 GNDP MSA6 MSA7 MSA8 MSA9 MSA10 VDDP MSA11 MSA12 TXCLK TXEN GNDP NC
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
MX98743
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
NC NC CPUD5 CPUD4 VDDP CPUD3 CPUD2 CPUD1 CPUD0 GNDP RESET GND INT RDY R/W VDDP CS RS0 RS1 RS2 RS3 GNDP RS4 RS5 RS6 RS7 RS8 VDDP RS9 RS10 RS11 RS12 DWS1 DWS0 GNDP NC
Figure 4-1. 144 Pin PQFP Package
4
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MX98743
5.0 PIN DESCRIPTION
Table 5-1. Media Independent Interface, 15 pins
PIN# NAME I/O DESCRIPTION Receive Data Valid MII. Synchronous to RXCLK's rising edge. This signal remains asserted through the whole frame, starting with the start-of-frame delimiter and excluding any end-of-frame delimiter. Carrier Sense MII. This pin, synchronous to RXCLK in TX mode, is asserted when the receiving medium is not idle. Receive Error. This pin is synchronous to RXCLK's rising edge. While RXDV is asserted, i.e. a frame is being received, this signal is asserted if any coding error is detected. Receive Clock MII. 25 MHz continuous clock that provides the timing reference for the transfer of the RXDV, RXD and RXER signals. Receive Data MII. RXD3-0 are synchronous to RXCLK's rising edge with RXD3 being the Most Significant Bit. For each RXCLK period in which RXDV is asserted, RXD3-0 should be latched by the MAC. While RXDV is deasserted , RXD3-0 are the 5B/4B nibbles decoded from RDAT4-0. Collision Mll. This signal is asserted if both the receiving media and TXEN are active. 25 MHz Transmit Clock Input. Transmit Enable. This output becomes active when the first data packet is valid on TXD3-0 and goes low after the last packet is clocked out of TXD[3:0]. Transmit Data MII. TXD3-0 are synchronous to TXCLK's rising edge with TXD3 being the Most Significant Bit
15
RXDV
I, TTL
14
CRS
I, TTL
8
RXER
I. TTL
6
RXCLK
I, TTL
9-12
RXD3-0
I, TTL
7 141 142 1-4
COL TXCLK TXEN TXD[3:0]
I, TTL I, TTL O O
5
INDEX
MX98743
Table 5-2. Expansion Port, 8 pins
PIN# NAME I/O DESCRIPTION Activity Out. These pins, synchronous to the 50 MHz clock, represent the activities of each port and also serve as data framing signals for the packet on EDATA. ACT_P leads EDAT's /J/K pattem by more than 80ns and is deasserted 40 ns after the /T/R or the last byte of Jam patterns.
16,17, 20-25
ACTP[7:0]
I, TTL
Table 5-3. XRC Register Access Pins, 8 pins
PIN# NAME I/O DESCRIPTION Partition/Link Good. This pin, active high, shows the Patition and Link status of the repeater MX98741. The serial input data is stored in Register RS[12:1]=081h. JAB/Elastic Buffer Over/Underflow. This pin, active high, shows the Jabber status and Elastic Buffer Over/Underflow status of the XRC. The serial input data is stored in Register RS[12:1]=01Ah. Isolation. This pin shows the Isolation status of the XRC. The serial input data is stored in Register RS[12:1]=01Ch.
29
PARTLNK
I, TTL
30
JBFLO
I, TTL
28
ISO
I, TTL
6
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MX98743
Table 5-3. XRC Register Access Pins, 8 pins
PIN# NAME I/O DESCRIPTION Port Enable/Scramble Enable. If XRCR/W is high, each port's Enable/Scramble status is displayed at the rising edge of REGCK and the serial input data is stored in Register RS[12:1]=016h. If XRCRW is low, the content of Register RS[12:1]=016h is read out serially. Isolation/Partition Disable. If XRCR/W is high, each port's Isolation/Partition status is displayed at the rising edge of REGCK and the serial input data is stored in Register RS[12:1]=01Eh. If XRCRW is low, the content of Register RS[12:1]=01Eh is read out serially. XRC Read or Write. High indicates 'Read' Mode; register is being read out. Low indicates 'Write' Mode. The FEM will issue XRC register write cycle when the CPU is writing Register RS[12:1]=016h or 01Eh.
31
PTSCEN
I/O
32
IPDIS
I/O
34
XRCR/W
O, TTL
35
REGLCH
Register Latch. REGLCH is an input pin when XRCRW is held high and an I/O, TTL output pin when XRCRW is held low. Register Clock . This pin is providing the 12.5MHz frequency whenever the FEM is accessing the XRC registers.
36
REGCK
O
7
INDEX
MX98743
Table 5-4. CPU Interface, 51 pins
PIN# 56 58 59 60 NAME CS R/W RDY INT I/O I,TTL I,TTL O,OD O,OD DESCRIPTION Chip Select. This pin, active low, is used to access the FEM internal register or SRAM buffer when held low. System Read/Write. High for read, and low for write. Ready. This pin, active low, is an tri-state output. Interrupt. Active low. Open Drain. Data. A group of 8,16, or 32 pins can become active depending on the value of DWS1-0. Inactive pins are tri-stated.
64-67, 69, 70, 73, 74, 76-79, 82-85, CPUD0-31 87-90, 93-95, 98-101, 103-106
I/O
40-39,
DWS[1:0]
I,TTL
Datapath Width Selection. These two pins determin which datapath width for CPUD31-0. DWS[1:0] = '00' : 8 bit, = '01' or '10' : 16 bit, = '11' : 32 bit. FEM Register or CPU Selection. When RS12=0, RS[11:0] represents FEM internal registers select pins. When RS12=1, RS[11:0] represents CPU interface address lines. RS[11:0] is mapped to MA[11:0] for 4Kbytes memory: 0h~7ffh for receive buffer, and 800h~fffh for transmit buffer.
41-44, 46-50, 52-55
RS12-0
I,TTL
8
INDEX
MX98743
Table 5-5. SRAM Interface, 24 pins
PIN# NAME I/O DESCRIPTION SRAM Address. 13-bit address to select the minimum 8Kbytes memory. O
140, 139, 137-133, MSA[12:0] 131-128, 126-125 112-115, 118-121 124 123 110 MD[7:0] MOEX_ MWEX_ CLK50M
I/O, TTL O O I, TTL
SRAM Data Bus. SRAM Read Enable. Active low. SRAM Write Enable. Active low. 50 MHz Oscillator Input. This is the clock reference for SRAM Interface bus timing.
Table 5-6. Miscellaneous Pins, 2 pin
PIN# 62 111 NAME RESET TEST I/O I, TTL I, TTL DESCRIPTION Reset. Reset is active low and places all the MX98743 logic in a reset mode. Test Pin. This is the internal test pin which is internal pulled low. User can either leave it uncommented or tie it to ground for normal operation.
9
INDEX
MX98743
Table 5-7. Power/Ground, 30 pins
PIN# NAME I/O Ground. DESCRIPTION
13, 26, 27 38, 51, 61, 63, 75, 86, GND/GNDP 96, 97, 107, 122, 132, 143 5, 18, 19, 33, 45, 57, 68, 80, 81, 91, 102, 116, 117, 127,138
Power.
VDD/VDDP
Table 5-7. No Connection, 6 pins
PIN# 37, 71, 72, 108, 109, 144 NAME I/O DESCRIPTION No Connection. Do not connected to these pins. NC
10
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MX98743
6.0 SRAM BUFFER OPERATION
6.1 RECEIVE & TRANSMIT PAGE FORMAT
SRAM Map consists a total of 8K bytes memory which is divided equally into 4 pages. Each Page is 12K bytes; there are three received pages and one transmit page. The Receive buffer uses a Buffer Ring Structure comprised of three ontiguous 2K-byte buffers, Page 0-2, for storage of received packet.
RX Page 0 (2K bytes) RX Page 1 (2K bytes) RX Page 2 (2K bytes) TX Page (2K bytes)
The first two bytes of each Receive Page is used to store the receive status. Byte0 contains Receive Byte Count--Countbit[7:0]; while byte1 contains various information as follows:
Byte0 & Byte1
BIT DESCRIPTION
byte 1[7:0] Receive byte count -- Countbit[7:0] byte 1[7] byte 1[6] byte 1[5] byte 1[4] Packet received with no error. CRC error. Multicast/Broadcast or Physical Address. Internal four-byte FIFO overrun.
byte 1[3:0] Receive byte count -- Countbit[11:8]
The first word if the Transmit Page contains the transmit byte count information with byte0--Countbit[7:0] and byte 1[3:0]--Countbit[11:8].
11
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MX98743
6.2 Receive Buffer Ring
Two pointers are used to control the Receive Buffer Ring. These are the Current Page Number Pointers and the Select Page Number Pointer. The Current Number Pointer points to the first Page that MAC will use to update the received data, whereas the Select Page Number Pointer points to the first page in the Ring not yet read by the CPU. Under normal operation, the CPU activates Receive Enable Bit in the Register 3C(MAC Control Register) and the packet beings arriving. The MAC starts storing the packet at the location pointed to be the Current Page Number Pointer. If three packets have successfully arrived the Buffer Ring and the CPU has not read a single page from the SRAM, the values of the Current and the Select Page Number are equal. As a result, the Receive Enable bit is disable and it remains disabled untile the CPU has removed at least one Packet data from the Ring to advance the Select Page Number Pointer. Each time a packet is successfully written on the SRAM, an interrupt is issued. The CPU will acknowledge interrupt and removes a packet from the Buffer Ring where the Select Page Number Pointer is point to. Usually the Select Page Number Pointer will advance when a packet is removed. If the values of Select Page Number and the Current Page Number are not equal, CPU will continue reading data from the Buffer Ring. However, if the values are equal, CPU will abort reading activity. The following procedures better illustrates how CPU handles different Receive Buffer Ring situations: Initial Receive Enable procedure: 1. Get Current Page Number from the MAC Status Register. 2. Assign Select Page Number the value of Current Page Number and set Receive Enable bit. Procedure During Normal Receive Operation: 1. If Select Page Number dose not equal to the Current Page Number, go to step 2. 2. Read Receive Buffer Ring data. 3. Assign Select Page Number to the next page. 4. Go back to step 1. Procedure For Receive Buffer Overflow: 1. Read the Receive Buffer data. 2. Assign Select Page Number to the next page. 3. Read Receive Buffer data. 4. Assign Select Page Number to the next page. 5. Read Receive Buffer data. 6. Assign the Select Page Number to the next page. 7. Re-initial receive enable procedure.
12
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MX98743
Receive Enable Bit Set RX Page 0 Select Page Number RX Page 1 RX Page 2 Current Page Number
Figure 6-1. Receive Buffer Ring
Receive Enable Bit Cleared RX Page 0 Select Page Number RX Page 1 RX Page 2 Current Page Number
Figure 6-2. Received Packet Enters the Buffer Ring
Receive Enable Bit Set RX Page 0 RX Page 1 Select Page Number RX Page 2 Current Page Number
Figure 6-3. CPU Removed One Packet from the Buffer Ring
13
INDEX
MX98743
7.0 Programming Guide
All the FEM registers, attributes as well as XRC registers can be accessed through the CPU interface directly with indexing. All registers are 16-bit wide and mapped directly to RS[12:0] is used to determine FEM Register selection or SRAM access. RS12=0 indicates FEM register select; RS12=1 indicates SRAM access. For SRAM access, RS[11:0] is mapped to MA[11:0] for 4Kbyte memory; 0h-7ffh for receive buffer, 800h-fffh for transmit buffer.
7.1 GENERAL DESCRIPTION OF REGISTER ACCESS METHODS
Each entry in the following tables represents a 16-bit wide register space. Only RS0 is used to selected the bytes within the 16-bit register if the datapath is 8-bit wide; however, RS[12:2] are needed to access the registers if 32-bit datapath is selected.
7.2 SRAM ACCESS & FEM REGISTER SELECTION TABLE Table 6-1. SRAM Access & FEM Register Selection Table
RS12 RS11 RS[10:8] RS[7:1] 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 0 0 0 0 0 0 x x 00 02 04 06 08 0A 0C 0E 12 14 RS0 x x x x x x x x x x x x REGISTER SRAM Access, 0-7ffh:Receive Buffer SRAM Access, 800-fffh:Transmit Buffer Repeater Interrupt Status Register Repeater Interrupt Mask Register Port Link/Partition Change Interrupt Status Register Port Link/Partition Change Interrupt Mask Register Data Rate Mismatch/Jabber Interrupt Status Register Data Rate Mismatch/Jabber Interrupt Mask Register Isolation/SA Change Interrupt Status Register Isolation/SA Change Interrupt Mask Register Sample Period Register Sample Enable Register R/W R/W R/W R R/W R R/W R R/W R R/W R/W R/W
14
INDEX
MX98743
Table 6-1. SRAM Access & FEM Register Selection Table
RS12 RS11 RS[10:8] RS[7:1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 16 18 1A 1C 1E 22 24 26 28 2A 2C 30 32 34 36 38 3A 3C 3E 00-6F 00-6F 00-6F 00-6F 00-6F 00-6F 00-6F 00-6F RS0 x x x x x x x x x x x x x x x x x x x x x x x x x x x REGISTER XRC Port Control Register Link and Partition Status Register EB O/U and Jabber Status Register Isolation Status Partition/Isolation Disable Status Stored SA Lo for SA Match Interrupt Stored SA Mid for SA Match Interrupt Stored SA Hi for SA Match Interrupt Stored DA Lo for DA Match Interrupt Stored DA Mid for DA Match Interrupt Stored DA Hi for DA Match Interrupt Stored SA1 Lo for Management Packet Received Stored SA1 Mid for Management Packet Received Stored SA1 Hi for Management Packet Received Stored SA2 Lo for Management Packet Received Stored SA2 Mid for Management Packet Received Stored SA2 Hi for Management Packet Received MAC Control Register MAC Status Register Port 0 802.3 Attributes and RMON MIBs Port 1 802.3 Attributes and RMON MIBs Port 2 802.3 Attributes and RMON MIBs Port 3 802.3 Attributes and RMON MIBs Port 4 802.3 Attributes and RMON MIBs Port 5 802.3 Attributes and RMON MIBs Port 6 802.3 Attributes and RMON MIBs Port 7 802.3 Attributes and RMON MIBs R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
15
INDEX
MX98743
Table 6-2. IEEE Attributes and RMON MIB Selection Table
RS[7:1] 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 20 21 22 23 23-2F RS0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x IEEE Attributes dot3 Readable Frames Lo dot3 Readable Frames Hi dot3 Readable Octets Lo dot3 Readable Octets Hi dot3 Frame Check Sequence Errors Lo dot3 Frame Check Sequence Errors Hi dot3 Aligment Errors Lo dot3 Aligment Errors Hi dot3 Frame Too Long Lo dot3 Frame Too Long Hi dot3 Short Events Lo dot3 Short Events Hi dot3 Runts Lo dot3 Runts Hi dot3 Collision Lo dot3 Collision Hi dot3 Late Event Lo dot3 Late Event Hi dot3 Very Long Events Lo dot3 Very Long Events Hi dot3 Data Rate Mismatches Lo dot3 Data Rate Mismatches Hi dot3 Auto Partitions Lo dot3 Auto Partitions Hi dot3 Isolates Lo dot3 Isolates Hi dot3 Symbol Error During packet Lo dot3 Symbol Error During packet Hi dot3 Last Source Address Lo dot3 Last Source Address Mid dot3 Last Source Address Hi dot3 Source Address Change Lo dot3 Source Address Change Hi dot3 False Carriers Lo dot3 False Carriers Hi reserved R/W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R/W R/W R/W R R R R
16
INDEX
MX98743
Table 6-3. RMON MIB Selection Table
RS[7:1] 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 RS0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x IEEE Attributes Rmon Ether Stats Drop Events Lo Rmon Ether Stats Drop Events Hi Rmon Ether Stats Octets Lo Rmon Ether Stats Octets Hi Rmon Ether Stats Pkts Lo Rmon Ether Stats Pkts Hi Rmon Ether Stats Broadcast Pkts Lo Rmon Ether Stats Broadcast Pkts Hi Rmon Ether Stats Multicast Pkts Lo Rmon Ether Stats Multicast Pkts Hi Rmon Ether Stats CRC Align Errors Lo Rmon Ether Stats CRC Align Errors Hi Rmon Ether Stats Undersized Pkts Lo Rmon Ether Stats Undersized Pkts Hi Rmon Ether Stats Oversized Pkts Lo Rmon Ether Stats Oversized Pkts Hi Rmon Ether Stats Fragments Lo Rmon Ether Stats Fragments Hi Rmon Ether Stats Jabbers Lo Rmon Ether Stats Jabbers Hi Rmon Ether Stats Collision Lo Rmon Ether Stats Collision Hi Rmon Ether Stats Pkts 64 Octets Lo Rmon Ether Stats Pkts 64 Octets Hi Rmon Ether Stats Pkts 65 to 127 Octets Lo Rmon Ether Stats Pkts 65 to 127 Octets Hi Rmon Ether Stats Pkts 128 to 255 Octets Lo Rmon Ether Stats Pkts 128 to 255 Octets Hi Rmon Ether Stats Pkts 236 to 511 Octets Lo Rmon Ether Stats Pkts 236 to 511 Octets Hi Rmon Ether Stats Pkts 512 to 1023 Octets Lo Rmon Ether Stats Pkts 512 to 1023 Octets Hi Rmon Ether Stats Pkts 1024 to 1518 Octets Lo Rmon Ether Stats Pkts 1024 to 1518 Octets Hi Rmon Ether History Drop Events Lo Rmon Ether History Drop Events Hi Rmon Ether History Octets Lo R/W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
17
INDEX
MX98743
Table 6-3. RMON MIB Selection Table
RS[7:1] 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 RS0 x x x x x x x x x x x x x x x x x x x RMON MIB Rmon Ether History Octets Hi Rmon Ether History Pkts Lo Rmon Ether History Pkts HI Rmon Ether History Broadcast Pkts Lo Rmon Ether History Broadcast Pkts Hi Rmon Ether History Multicast Pkts Lo Rmon Ether History Multicast Pkts Hi Rmon Ether History CRC Align Errors Lo Rmon Ether History CRC Align Errors Hi Rmon Ether History Undersized Pkts Lo Rmon Ether History Undersized Pkts Hi Rmon Ether History Oversized Pkts Lo Rmon Ether History Oversized Pkts Hi Rmon Ether History Fragments Lo Rmon Ether History Fragments Hi Rmon Ether History Jabbers Lo Rmon Ether History Jabbers Hi Rmon Ether History Collision Lo Rmon Ether History Collision Hi R/W R R R R R R R R R R R R R R R R R R R
18
INDEX
MX98743
8.0 REGISTER DEFINITIONS
8.1 MAC CONTROL REGISTER (R/W)
msb 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8 X 7 RB 6 5 4 S1 3 S0 2 X 1 X lsb 0 TEN
RM REN
Table 7-1.
BIT 15:8 7 6 NAME Reserved RB RM Reserved 1: Receive brocast packet. 0: Not to eceive brocast packet. 1: Receive multicast packet. 0: Not to receive multicast packet. 1: Receive enable. It is cleared whenreceive buffer overflows or the FEM is in reset state. 0: Receive disable. Select page number of receive buffer for CPU access. [S1,S0] = 00: Page 0; 01: Page 1; 1x: Page 2. Reserved TEN 1:Transmit enable. It is cleared by packet transmitted to FEM reset. 0:Transmit disable. DESCRIPTION R/W R/W R/W R/W
5
REN
R/W
4-3
S1-0
R/W
2-1 0
R/W R/W
19
INDEX
MX98743
8.2 MAC STATUS REGISTER (R)
msb 15 TX 14 13 12 11 UR 10 X 9 X 8 X 7 RX 6 5 4 OR 3 BF 2 ABT 1 S1 lsh 0 S0
COL ABT CRS
CRC MB
Table 7-2.
BIT 15 14 13 12 11 10-8 7 6 5 4 3 2 1-0 NAME TX COL ABT CRS UN X RX CRC MB OR BF ABT S1-0 DESCRIPTION 1:Packet transmitted with no errors. 1: Collision at least once. 1: Transmit is aborted after 16 collisions. 1: Carrier sense lost during transmission. 1:Internal 4 bytes FIFO underrun. Reserved 1:Packet received with no errors. 1:CRC error. 1:Multicast/Broadcast Address match. 0:Physical Address match. 1:Internal 4 bytes FIFO overrun. 1:Receive Buffer Full. 1:Packet aborted due to Receive Buffer full. Current Page Number of Receive Buffer for MAC receiver. R/W R R R R R R R R R R R R R
20
INDEX
MX98743
8.3 REPEATER INTERRUPT STATUS REGISTER (RO)
msb 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8 X 7 GI 6 IE 5 SA 4 DA 3 X 2 TX 1 RX lsb 0 X
Table 7-3.
BIT 15:8 NAME Reserved Indeterminate Global Interrupt. 1:INT is not active. 0:INT is active. This bit becomes '1' only if all the interrupt sources are cleared. Interface Error Interrupt. Set to '1' if interface error with XRC occurs. Source Address Match Interrupt. The SA of incoming packet matches a pre-defined 6-byte DA value. Destination Address Match Interrupt. The DA of incoming packet matches a pre-defined 6-byte DA value. Indeterminate Management Packet Transmitted. 1:Packet transmitted. It is clear after reset. 0:No packet transmitted. Management Packet Received. 1:Packet received. It is cleared after reset. Reserved DESCRIPTION R/W R
7
G
R
6 5 4 3 2
I S D Reserved TX
R R R R R
1 0
RX Reserved
R R
21
INDEX
MX98743
8.4 REPEATER INTERRUPT MASK/CONFIGURATION REGISTER (R/W)
msb 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8 X 7 GM 6 IM 5 SM 4 DM 3 X 2 TM 1 RM lsb 0 RS
Table 7-4.
BIT 15:8 7 NAME Reserved GM Indeteminate Global Interrupt Mask. 1:Masking INT. 0:Unmasking INT. Interface Error Interrupt Mask. 1:Masking INT. 0:Unmasking INT Source Address Match Interrupt Mask. 1:Masking INT. 0:Unmasking INT Destination Address Match Interrupt Mask. 1:Masking INT. 0:Unmasking INT Indeterminate Management Packet Transmitted Interrupt Mask. 1:Masking INT. 0:Unmasking INT Management Packet Received Interrupt Mask. 1:Masking INT. 0:Unmasking INT 1:Reset FEM. 0:Not Reset FEM. '0' after RESET pin is asserted low. DESCRIPTION R/W R/W R/W
6
IM
R/W
5
SM
R/W
4
DM
R/W
3 2
Reserved TM
R R/W
1
RM
R/W
0
RS
R/W
22
INDEX
MX98743
8.5 PORT LINK STATUS CHANGE/PARTITION INTERRUPT (RO)
msb 15 L7 14 L6 13 L5 12 L4 11 L3 10 L2 9 L1 8 L0 7 P7 6 P6 5 P5 4 P4 3 P3 2 P2 1 P1 lsb 0 P0
Table 7-5.
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME L7 L6 L5 L4 L3 L2 L1 L0 P7 P6 P5 P4 P3 P2 P1 P0 DESCRIPTION Set to '1' if Link Status changes on Port 7. Set to '1' if Link Status changes on Port 6. Set to '1' if Link Status changes on Port 5. Set to '1' if Link Status changes on Port 4. Set to '1' if Link Status changes on Port 3. Set to '1' if Link Status changes on Port 2. Set to '1' if Link Status changes on Port 1. Set to '1' if Link Status changes on Port 0. Set to '1' if Partition Status changes on Port 7. Set to '1' if Partition Status changes on Port 6. Set to '1' if Partition Status changes on Port 5. Set to '1' if Partition Status changes on Port 4. Set to '1' if Partition Status changes on Port 3. Set to '1' if Partition Status changes on Port 2. Set to '1' if Partition Status changes on Port 1. Set to '1' if Partition Status changes on Port 0. R/W R R R R R R R R R R R R R R R R
All bits are cleared after read and reset.
23
INDEX
MX98743
8.6 PORT LINK/PARTITION INTERRUPT MASK REGISTER (R/W)
msb
15 LM7 14 LM6 13 LM5 12 LM4 11 LM3 10 LM2 9 LM1 8 LM0 7 PM7 6 PM6 5 PM5 4 PM4 3 PM3 2 PM2 1 PM1
lsb
0 PM0
Table 7-6.
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME LM7 LM6 LM5 LM4 LM3 LM2 LM1 LM0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 DESCRIPTION 1:Mask Link Status change interrupt on Port 7. 0:Unmask Link Status change Interrupt on Port 7. 1:Mask Link Status change interrupt on Port 6. 0:Unmask Link Status change Interrupt on Port 6. 1:Mask Link Status change interrupt on Port 5. 0:Unmask Link Status change Interrupt on Port 5. 1:Mask Link Status change interrupt on Port 4. 0:Unmask Link Status change Interrupt on Port 4. 1:Mask Link Status change interrupt on Port 3. 0:Unmask Link Status change Interrupt on Port 3. 1:Mask Link Status change interrupt on Port 2. 0:Unmask Link Status change Interrupt on Port 2. 1:Mask Link Status change interrupt on Port 1. 0:Unmask Link Status change Interrupt on Port 1. 1:Mask Link Status change interrupt on Port 0. 0:Unmask Link Status change Interrupt on Port 0. 1:Mask Partition Status change interrupt on Port 7. 0:Unmask Partition Status change Interrupt on Port 7. 1:Mask Partition Status change interrupt on Port 6. 0:Unmask Partition Status change Interrupt on Port 6. 1:Mask Partition Status change interrupt on Port 5. 0:Unmask Partition Status change Interrupt on Port 5. 1:Mask Partition Status change interrupt on Port 4. 0:Unmask Partition Status change Interrupt on Port 4. 1:Mask Partition Status change interrupt on Port 3. 0:Unmask Partition Status change Interrupt on Port 3. 1:Mask Partition Status change interrupt on Port 2. 0:Unmask Partition Status change Interrupt on Port 2. 1:Mask Partition Status change interrupt on Port 1. 0:Unmask Partition Status change Interrupt on Port 1. 1:Mask Partition Status change interrupt on Port 0. 0:Unmask Partition Status change Interrupt on Port 0. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
All bits are cleared after reset
24
INDEX
MX98743
8.7 DATA RATE MISMATCH/JABBER INTERRUPT (RO)
msb 15 O7 14 O6 13 O5 12 O4 11 O3 10 O2 9 O1 8 O0 7 J7 6 J6 5 J5 4 J4 3 J3 2 J2 1 J1 lsb 0 J0
Table 7-7.
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME O7 O6 O5 O4 O3 O2 O1 O0 J7 J6 J5 J4 J3 J2 J1 J0 DESCRIPTION Set to '1' if Elastic Buffer Over/Underflow on Port 7. Set to '1' if Elastic Buffer Over/Underflow on Port 6. Set to '1' if Elastic Buffer Over/Underflow on Port 5. Set to '1' if Elastic Buffer Over/Underflow on Port 4. Set to '1' if Elastic Buffer Over/Underflow on Port 3. Set to '1' if Elastic Buffer Over/Underflow on Port 2. Set to '1' if Elastic Buffer Over/Underflow on Port 1. Set to '1' if Elastic Buffer Over/Underflow on Port 0. Set to '1' if Jabber occurs on Port 7. Set to '1' if Jabber occurs on Port 6. Set to '1' if Jabber occurs on Port 5. Set to '1' if Jabber occurs on Port 4. Set to '1' if Jabber occurs on Port 3. Set to '1' if Jabber occurs on Port 2. Set to '1' if Jabber occurs on Port 1. Set to '1' if Jabber occurs on Port 0. R/W R R R R R R R R R R R R R R R R
All bits are cleared after read and reset.
25
INDEX
MX98743
8.8 DATA RATE MISMATCH/JABBER INTERRUPT MASK REGISTER (R/W)
msb
15 O7 14 O6 13 O5 12 O4 11 O3 10 O2 9 O1 8 O0 7 J7 6 J6 5 J5 4 J4 3 J3 2 J2 1 J1
lsb
0 J0
Table 7-8.
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME OM7 OM6 OM5 OM4 OM3 OM2 OM1 OM0 JM7 JM6 JM5 JM4 JM3 JM2 JM1 JM0 DESCRIPTION 1:Mask Buffer Over/Underflow interrupt on Port 7. 0:Unmask Buffer Over/Underflow Interrupt on Port 7. 1:Mask Buffer Over/Underflow interrupt on Port 6. 0:Unmask Buffer Over/Underflow Interrupt on Port 6. 1:Mask Buffer Over/Underflow interrupt on Port 5. 0:Unmask Buffer Over/Underflow Interrupt on Port 5. 1:Mask Buffer Over/Underflow interrupt on Port 4. 0:Unmask Buffer Over/Underflow Interrupt on Port 4. 1:Mask Buffer Over/Underflow interrupt on Port 3. 0:Unmask Buffer Over/Underflow Interrupt on Port 3. 1:Mask Buffer Over/Underflow interrupt on Port 2. 0:Unmask Buffer Over/Underflow Interrupt on Port 2. 1:Mask Buffer Over/Underflow interrupt on Port 1. 0:Unmask Buffer Over/Underflow Interrupt on Port 1. 1:Mask Buffer Over/Underflow interrupt on Port 0. 0:Unmask Buffer Over/Underflow Interrupt on Port 0. 1:Mask Jabber interrupt on Port 7. 0:Unmask Jabber Interrupt on Port 7. 1:Mask Jabber interrupt on Port 6. 0:Unmask Jabber Interrupt on Port 6. 1:Mask Jabber interrupt on Port 5. 0:Unmask Jabber Interrupt on Port 5. 1:Mask Jabber interrupt on Port 4. 0:Unmask Jabber Interrupt on Port 4. 1:Mask Jabber interrupt on Port 3. 0:Unmask Jabber Interrupt on Port 3. 1:Mask Jabber interrupt on Port 2. 0:Unmask Jabber Interrupt on Port 2. 1:Mask Jabber interrupt on Port 1. 0:Unmask Jabber Interrupt on Port 1. 1:Mask Jabber interrupt on Port 0. 0:Unmask Jabber Interrupt on Port 0. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
All bits are cleared after reset
26
INDEX
MX98743
8.9 ISOLATION/SA CHANGE INTERRUPT (RO)
msb 15 I7 14 I6 13 I5 12 I4 11 I3 10 I2 9 I1 8 I0 7 S7 6 S6 5 S5 4 S4 3 S3 2 S2 1 S1 lsb 0 S0
Table 7-9.
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME O7 O6 O5 O4 O3 O2 O1 O0 J7 J6 J5 J4 J3 J2 J1 J0 DESCRIPTION Set to '1' if Isolation occurs on Port 7. Set to '1' if Isolation occurs on Port 6. Set to '1' if Isolation occurs on Port 5. Set to '1' if Isolation occurs on Port 4. Set to '1' if Isolation occurs on Port 3. Set to '1' if Isolation occurs on Port 2. Set to '1' if Isolation occurs on Port 1. Set to '1' if Isolation occurs on Port 0. Set to '1' if Source occurs on Port 7. Set to '1' if Source occurs on Port 6. Set to '1' if Source occurs on Port 5. Set to '1' if Source occurs on Port 4. Set to '1' if Source occurs on Port 3. Set to '1' if Source occurs on Port 2. Set to '1' if Source occurs on Port 1. Set to '1' if Source occurs on Port 0. R/W R R R R R R R R R R R R R R R R
All bits are cleared after read and reset.
27
INDEX
MX98743
8.10 ISOLATION/SA CHANGE INTERRUPT MASK REGISTER (R/W)
msb
15 IM7 14 IM6 13 IM5 12 IM4 11 IM3 10 IM2 9 IM1 8 IM0 7 SM7 6 SM6 5 SM5 4 SM4 3 SM3 2 SM2 1 SM1
lsb
0 SM0
Table 7-10.
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0 DESCRIPTION 1:Mask Isolation interrupt on Port 7. 0:Unmask Isolation Interrupt on Port 7. 1:Mask Isolation interrupt on Port 6. 0:Unmask Isolation Interrupt on Port 6. 1:Mask Isolation interrupt on Port 5. 0:Unmask Isolation Interrupt on Port 5. 1:Mask Isolation interrupt on Port 4. 0:Unmask Isolation Interrupt on Port 4. 1:Mask Isolation interrupt on Port 3. 0:Unmask Isolation Interrupt on Port 3. 1:Mask Isolation interrupt on Port 2. 0:Unmask Isolation Interrupt on Port 2. 1:Mask Isolation interrupt on Port 1. 0:Unmask Isolation Interrupt on Port 1. 1:Mask Isolation interrupt on Port 0. 0:Unmask Isolation Interrupt on Port 0. 1:Mask SA Change interrupt on Port 7. 0:Unmask SA Change Interrupt on Port 7. 1:Mask SA Change interrupt on Port 6. 0:Unmask SA Change Interrupt on Port 6. 1:Mask SA Change interrupt on Port 5. 0:Unmask SA Change Interrupt on Port 5. 1:Mask SA Change interrupt on Port 4. 0:Unmask SA Change Interrupt on Port 4. 1:Mask SA Change interrupt on Port 3. 0:Unmask SA Change Interrupt on Port 3. 1:Mask SA Change interrupt on Port 2. 0:Unmask SA Change Interrupt on Port 2. 1:Mask SA Change interrupt on Port 1. 0:Unmask SA Change Interrupt on Port 1. 1:Mask SA Change interrupt on Port 0. 0:Unmask SA Change Interrupt on Port 0. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
28
INDEX
MX98743
8.11 SAMPLE PERIOD REGISTER
msb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lsb 0
CT15 CTI4 CT13 CT12 CT11 CT10 CT9 CT8 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0
The 16-bit value which determines the length of the sample period in seconds in seconds in RMON f\history group is loaded into the sampling state machine whenever it is enabled. The maximum sampling window is 65536 seconds.
8.12 SAMPLE ENABLE REGISTER
msb 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X lsb 0 SME
Table 7-9.
BIT 15:1 NAME Reserved. 1:This bit is used to enable the sampling state machine and is self-cleared at the end of the sampling period. 0:Sampling state machine is in the idle state. After reset, this bit is '0'. DESCRIPTION R/W
0
SME
R/W
8.13 XRC REGISTERS
Refer to MX98741 XRC 100BASE TX/FX repeater specification Section 8.
29
INDEX
MX98743
8.14 BIT ACCESS ORDER
In the address table, 16-bit register format are used. However, the addresses are assigned in such a way that in 32-bit mode, on it RS[11:2] are needed, and in 8-bit mode, RS[11:0] are needed.
32-bit Access 16-bit register access (RS 11='0')
msb D31 D16 D15
lsb D0
32-bit counter access (RS11='1')
msb D31
Hi
lsb D16
msb D15
Lo
lsb D0
48-bit Last SA access
Last SA Mid D31 D16 D15
Last SA Lo D0
Last SA Hi D31 D16 D15 D0
30
INDEX
MX98743
16-bit Access 16-bit Register Access
Interrupt Register etc. MSB D15 D8 D7 LSB D0
32-Bit Register Access
MIB Lo MSB D15 D8 D7 LSB D0
MIB Hi MSB D15 D8 D7 LSB D0
31
INDEX
MX98743
48-Bit Last SA Access SA Lo SA Byte 1 LSB D15 D8 MSB D7 I/G U/L D0 SA Byte 0
SA Mid SA Byte 3 LSB D15 D8 MSB D7 LSB SA Byte 2 MSB D0
SA Hi SA Byte 5 LSB D15 D8 MSB D7 LSB SA Byte 4 MSB D0
32
INDEX
MX98743
8-bit Access 16-bit Register Access
Interrupt Register etc. MSB D7 RS0='1' D0 D7 RS0='0' D0 LSB
32-Bit Register Access
MIB Lo MSB D7 RS0='1' D0 D7 RS0='0' D0 LSB
MIB Hi MSB D7 RS0='1' D0 D7 RS0='0' D0 LSB
33
INDEX
MX98743
48-Bit Last SA Access SA Lo
SA Byte 1, RS0='1' LSB D7 D0 MSB D7 I/G
SA Byte 0, RS0='0' U/L D0
SA Mid SA Byte 3, RS0='1' LSB D7 D0 MSB D7 LSB SA Byte 2, RS0='1' MSB D0
SA Hi SA Byte 5, RS0='1' LSB D7 D0 MSB D7 LSB SA Byte 4, RS0='1' MSB D0
34
INDEX
MX98743
9.0 ABSOLUTE MAXIMUM RATINGS
Table 10-1. Absolute Maximum Ratings
RATING SupplyVoltage (VCC) DC Input Voltage (Vin) DC Output Voltage (Vout) Storage Temperature Range (TSTG) Power Dissipation (PD) ESD Rating (Rzap=1.5K, Czap=100pF) VALUE 4.75 V to 5.25 V -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V -55C to 150 C 600 mW 2000 V
Note : 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Preliminary, subject to change.
10.0 DC CHARACTERISTICS
Table 10-1. Supply Current
SYMBOL ICC ICCIDLE IDD PARAMETER Average Active (TXing/ RXing) Supply Current Average Idle Supply Current Static IDD Current CONDITIONS VIN=Switching COCLK=50 MHz VIN=VCC/GND COCLK=Undriven MIN. TBD (note) TBD (note) MAX. UNIT mA mA uA
Note : These two parameters will be measured while DC/AC characterization is proceeding.
35
INDEX
MX98743
Table 10-2. TTL Inputs, Outputs, Tri-States Excluding CPU Interface
SYMBOL Vil Vih lin Voh Vol loz PARAMETER Maximum Low Level Input Voltage Minimum High Level Input Voltage Input Current Minimum High Level Input Voltage Maximum High Level Input Voltage Maximum Tri-State Output Leakage Current VI=VCC/GND loh=-2mA lol=2mA VOUT=VCC/GND CONDITIONS GND=0V MIN. 2.0 -1.0 2.4 -10.0 MAX. 0.8 VCC + 0.5 1.0 0.4 10.0 UNIT V V uA V V uA
10-3. CPU Inputs/Outputs, Tri-State, Open-drain
SYMBOL Voh Vol Vil Vih loz PARAMETER Maximum High Level Input Voltage Minimum Low Level Input Voltage Minimum Low Level Input Voltage Maximum High Level Input Voltage Maximum Tri-State Output Leakage Current VOUT=VCC/GND 2.0 -10.0 10.0 CONDITIONS loh=-4mA loh=-4mA MIN. 2.4 MAX. 0.4 0.8 UNIT V V V V uA
36
INDEX
MX98743
11.0 AC CHARACTERISTICS
T11 CLK50M
Figure 11-1. Clock CLK50M Timing
SYMBOL T11
PARAMETER SRAM bus clock period
MIN. 20
MAX. 33
UNIT ns
RXCLK T11 REGCK REGLCH PTSCEN IPDIS PARTLNK JBFLO, ISO T31 REGLCH PTSCEN IPDIS Output Data Input Data T21 T22
Figure 11-2. XRC Register Read & Write Cycle
SYMBOL T11 T21 T22 T31
PARAMETER RXCLK rising to REGCK high PTSCEN setup time PTSCEN hold ttime REGCL low to PTSCEN valid
MIN.
MAX. 6
UNIT ns ns ns
10 10 5
ns
37
INDEX
MX98743
RW
CS T11 RDY T21 CPUD T22 T21
Figure 11-3. CPU Read Cycle
SYMBOL T11 T12 T21 T22
PARAMETER CS active to RDY high CS inactive to RDY tristated CPUD to RDY active setup time CS inactive to CPUD tristated
MIN.
MAX. 6 2
UNIT ns ns ns
70 2
ns
38
INDEX
MX98743
RW CS T11 RDY T21 CPUD T22 T21
Figure 11-4. CPU Write Cycle
SYMBOL T11 T12 T21 T22
PARAMETER CS active to RDY high CS inactive to RDY tristated CPUD active to CPUD valid CS inactive to CPUD hold time
MIN.
MAX. 6 2 40
UNIT ns ns ns ns
6
39
INDEX
MX98743
CLK50M
MSA T11 T12 MOEX
Address
T21 T22 MD Data T23
Figure 11-5. SRAM Buffer Read
SYMBOL T11 T12 T21 T22 T23
PARAMETER MDA[12:0] MOEX asserted MSA[12:0] to MOEX inactive MOEX valid low pulse width MD valid to MOEX asserted setup time MD to MOEX asserted hold time
MIN. 1/2*TCLK-4 3/2*TCLK-6 TCLK-2 5 0
MAX.
UNIT ns ns ns ns ns
40
INDEX
MX98743
CLK50M
MSA T11 T12 MOEX
Address
T21 T22 MD Data T23
Figure 11-6. SRAM Buffer Write
SYMBOL T11 T12 T21 T22 T23
PARAMETER MSA[12:0] MOEX asserted MSA[12:0] to MOEX inactive MOEX valid low pulse width MD valid to MWEX asserted setup time MWEX asserted to MD tristated
MIN. 1/2*TCLK-4 3/2*TCLK-6 TCLK-2 3/2*TCLK-6 1/2*TCLK-4
MAX.
UNIT ns ns ns ns ns
41
INDEX
MX98743
12.0 PACKAGE INFORMATION
144-PIN QUAD FLAT PACK
ITEM A B C D E F G H I J K L M N O P
MILLIMETERS 31.2+/-0.3 28.0+/-0.1 28.0+/-0.1 31.2+/-0.3 22.75 2.63 [REF] 2.63 [REF] 0.30 [Typ.] 0.65 [Typ.] 1.60 [REF] 0.8+/-0.2 0.15 [Typ.] 0.10 max. 3.35 max. 0.10 min. 3.68 max.
INCHES 1.228+/-0.12 1.102+/-.004 1.102+/-.004 1.228+/-0.12 0.896 .103 [REF] .103 [REF] .012 [Typ.] .026 [Typ.] .063 [REF] .031+/-.008 .006 [Typ.] .004 max. .132 max. .004 min. .145 max.
Note:Each lead centerline is located within .25mm (.01 inch) of its true position [TP] at a maximum material condition.
42
INDEX
MX98743
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
No.3, Creation Road III, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. TEL:+886-3-578-8888 FAX:+886-3-578-8887
TAIPEI OFFICE:
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SINGAPORE OFFICE:
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MACRONIX AMERICA, INC.
1338 Ridder Park Drive, San Jose, CA95131 U.S.A. TEL:+1-408-453-8088 FAX:+1-408-453-8488
JAPAN OFFICE:
NFK Kawasaki Building, 8F, 1-2 Higashida-cho, Kawasaki-ku Kawasaki-shi, Kawasaki-ken 210, Japan TEL:+81-44-246-9100 FAX:+81-44-246-9105
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
43

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